CMPE 421 : Digital System Design - Suraj @ LUMS

CMPE 421 : Digital System Design (Tentative Outline) Instructor: Dr Shahid Masud Year: 2010-11 Credits: 3 Office: Room L302, SSE Building Email: smasud@lums.edu.pk Category: Senior / M.Sc. Semester: Fall Office Hours: Mon,
Tue, Wed 0900-1000 hrs ____________________________________________________________________ Course Description: This course explains how to go about designing complex, high-speed
digital systems. The use of modern EDA tools in the design, simulation and
implementation is explored. A hardware description language such as Verilog
or VHDL will be taught to model digital systems at Behavior and RTL level.
The field programmable gate arrays (FPGA) will be used in the laboratory
exercises as a vehicle to understand complete design-flow. Advanced methods
of logic minimization and state-machine design will be studied. The working
of complex logic and memory building blocks such as memory chips,
arithmetic circuits, digital processors, UARTs etc. is included. BIST and
Scan techniques for testing of digital systems are also discussed. Course Status:
Core course for B.Sc./M.Sc.Computer Engineering major
Elective course for B.Sc./M.Sc. Computer Science Pre-requisites:
Computer Organization and Assembly Language Goals:
Teach the design and implementation of digital systems using EDA tools
and FPGA
Text book:
Advanced Digital Design with the Verilog HDL by Michael D. Ciletti,
Prentice Hall, 2003 Supplementary:
1. Verilog HDL by Samir Palnitkar, Pearson Eduction, Second edition, 2004
2. Engineering Digital Design by Richard Tinder, Academic Press, Second
edition, 2000 Lectures and Examinations:
Two weekly lectures of 75 minutes duration each
One additional lab on Fridays
Attendance is not compulsory, punctuality is desired
One in-class midterm
One design exercise
Comprehensive final examination
TA for the course:
To be announced on course website
Grading Scheme:
. Quizzes (4): 15%
. Eight Labs for 10%, marks breakup is as follows:
. Attendance: 2%
. Completion: 4%
. Lab Exam: 4%
. One Design Exercise for 15%, marks breakup is as follows:
. Specifications: 2% (due before midterm exam)
. Coding and simulation testing: 5% (due one week before last
lecture)
. FPGA implementation and demonstration: 4% (due before last
lecture)
. Report on architecture and operation: 4% (due before last
lecture)
. Midterm: 30%
. Final: 30% Module Titles:
1. Introduction 1 week
2. Review of Combinational Logic Design 1 week
3. Logic Minimization by Quine-McCluskey 1 week
4. Sequential Logic Design 1 week
5. State Machine Minimization 1 week
6. Programmable Logic Devices 1 week
7. Architecture for Arithmetic Processors 1 week
8. Architecture for Digital Signal Processors 1 week
9. Design for test 1 week
10. Verilog concepts and techniques 1 week Lecture Topics:
|Lecture |Course Topics |Readings|
|No. | | |
|1 |Introduction to digital systems and their design|Chap 1 |
| |flow | |
|2 |Data Coding for Error Detection and Correction |Chap 4 |
|3 |Combinational Logic Design using MUX and |Chap 2 |
| |Decoders | |
|4 |Logic Minimisation techniques - Quine McCluskey |Chap 2 |
| |method | |
|5 |Glitches and Hazards |Chap 2 |
|6 |Lab 1: Introduction to Verilog | |
|7 |Lab 2: Simulations using Verilog | |
|8 |Lab 3: Behavioural and Structural Designs | |
|9 |Lab 4: RTL and FSM Synthesis | |
|10 |Delay Modelling Verilog techniques |Chap 4 |
|11 |Sequential Logic Design - Introduction |Chap 3 |
|12 |Moore and Mealy State Machines Design |Chap 3 |
|13 |State Minimization Techniques | |
|14 |Analysis of Asynchronous FSM | |
|15 |Midterm exam | |
|16 |Design of Asynchronous FSM | |
|17 |Programmable Logic Devices - PAL and CPLD |Chap 8 |
| |technology | |
|18 |FPGA from Xilinx and Altera - characteristics |Chap 8 |
|19 |Carry Lookahead Adders, Array Multipliers, |Chap 10 |
| |Critical Paths | |
|20 |Booth and Radix-4 Encoded Signed Multipliers |Chap 10 |
|21 |Controller Design for Sequential Multipliers and| |
| |Dividers | |
|22 |Signed Multiplication of Fractions, FIFO, |Chap 9 |
| |Frequency Generators | |
|23 |Faults and Testability - BIST and SCAN |Chap 11 |
| |techniques, Signatures | |
|24 |Design for test - JTAG |Chap 11 |
|25 |Lab 5: FPGA Implementation 1 | |
|26 |Lab 6: FPGA Implementation 2 | |
|27 |Lab 7: Design Exercises | |
|28 |Lab 8: Revision and Completion | |